The graphics subsystem hardware in a computing device typically includes several independent graphics engines. Software known as a graphics scheduler may be used to schedule the graphics engines to execute the graphics workloads that execute on the hardware. However, according to current techniques, the graphics scheduler is executed by the central processing unit (CPU) of the computing device. Executing the graphics scheduler on the CPU may impose significant latency overheads due to communication delays between the graphics engines and the CPU, which communicate via interrupts and memory-mapped input/output (MMIO) based programming. In addition, such communications between the CPU and the graphics engines may result in a large amount of power consumption, since the CPU may be forced to intermittently switch from a low power state to a high power state in order to perform scheduling operations.
The same numbers are used throughout the disclosure and the figures to reference like components and features. Numbers in the 100 series refer to features originally found in FIG. 1; numbers in the 200 series refer to features originally found in FIG. 2; and so on.